mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 49

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

SECTION 1
INTRODUCTION
The MPC823 microprocessor is a versatile, one-chip integrated microprocessor and
peripheral combination that can be used in a variety of portable electronic products. It is a
low-cost version of the MPC821 microprocessor, except it has been enhanced with
additional communication and display capabilities. Specifically, it supports the universal
serial bus and video display systems and the existing LCD interface on the MPC821 device.
The MPC823 microprocessor particularly excels in low-power, portable, image capture, and
personal communication products. It integrates a high-performance embedded PowerPC
core with a communication processor module that uses a specialized RISC processor for
imaging and communication. The communication processor module can perform embedded
signal processing functions for image compression and decompression and supports seven
serial channels—two serial communication controllers, two serial management controllers,
one I
two-processor architecture consumes power more efficiently than traditional architectures
because the communication processor module frees the core from peripheral
responsibilities like imaging and communication.
1.1 FEATURES
The following list summarizes the main features of the MPC823:
• Embedded PowerPC Core Provides 99MIPS (Using Dhrystone 2.1) or
• Advanced On-Chip Emulation Debug Mode
172K Dhrystones 2.1 at 75MHz
2
C port, one universal serial bus channel, and one serial peripheral interface. This
Single-Issue, 32-Bit Version of the PowerPC Core (Fully Compatible with the
PowerPC Architecture Definition) with 32 x 32-Bit Fixed-Point Registers
Low Power Consumption, 2.2V Internal, 3.3V I/O Boundary with Microprocessor
Core, Caches, Memory Management, and I/O in Operation
Performs Branch Folding, Branch Prediction with Conditional Prefetch, without
Conditional Execution
1K Data Cache and 2K Instruction Cache
Two-Way Instruction and Data Caches are Set-Associative, Physical Address,
4-Word Line Burst, LRU Replacement Algorithm, Lockable Online Granularity
Memory Management Units with 8-Entry Translation Lookaside Buffers (TLBs) and
Fully Associative Instruction and Data TLBs
Memory Management Units Support Multiple Page Sizes of 4K, 16K, 512K and 8M
(1K Protection Granularity at the 4K Page Size); 16 Virtual Address Spaces and
16 Protection Groups
MPC823 REFERENCE MANUAL
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