mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 215

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Data Cache
10.4.2.2 WRITETHROUGH MODE. In writethrough mode, store operations always update
memory. This mode is used when external memory and internal cache images must agree.
It gives a lower worst-case interrupt latency at the expense of average performance (for
example, if it does not have to do flush accesses). The possible outcomes of a data cache
write in writethrough mode are:
10.4.3 Data Cache Inhibited Accesses
If the cache access is to a page that has the CI bit set in the memory management unit, one
of the following outcomes will occur:
10.4.4 Data Cache Freeze
The MPC823 can be debugged either in debug mode or by a software monitor debugger.
The data cache is frozen when the freeze (FRZ) signal is asserted so that the data cache
can be examined for debugging purposes. For a detailed description of MPC823 debug
support, refer to Section 20 Development Capabilities and Interface. When FRZ is
asserted, the possible outcomes are:
• Write Hit—Data is written into both the cache and memory, but the cache state is not
• Write Miss—Data is only written into memory, not to the cache (write no allocate) and
• Hit to Modified or Unmodified Line—This is considered a programming error if the
• Read Miss—Data is read from memory, but not placed in the cache. The cache’s status
• Write Miss—Data is written through to memory, but not placed in the cache. The
• Read Miss—Data is read from memory, but not placed in the cache. The cache’s status
• Read Hit—Data is read from the cache, but LRU is not updated.
• Write Miss/Hit—Data cache operates in writethrough mode, but LRU is not updated.
• dcbz Instruction Miss/Hit—Data is written into cache and memory, but LRU is not
• dcbst/dcbf/dcbi Instructions—The data cache and memory is updated according to
changed. The LRU of the set is updated to point to the way holding the hit data. If a bus
error is detected during the write cycle, the cache is still updated and a machine check
interrupt is generated.
no state transition occurs. The LRU is not changed, but if a bus error is detected during
the write cycle, a machine check interrupt is generated.
targeted location copy of a load, store, or dcbz instruction to cache inhibit storage is in
the cache. The result is boundedly undefined.
is unaffected.
cache’s status is unaffected.
is unaffected.
updated.
the PowerPC architecture, but LRU is not updated.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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