mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 597

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Communication Processor Module
The MPC823 supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame
can be routed to every serial communication controller and serial management controller or
they can assert a strobe output that supports an external device.
The MPC823 supports the request-grant method for contention detection on the D channel
of the IDL basic rate and when the MPC823 has data to transmit on the D channel, it asserts
the L1RQ A pin. The physical layer device monitors the physical layer bus for activity on the
D channel and indicates that the channel is free by asserting the L1GRA pin. The MPC823
samples the L1GRA pin when the IDL sync signal (L1RSYNC A ) is asserted. If L1GRA is
high (active), the MPC823 transmits the first zero of the opening flag in the first bit of the D
channel. If a collision is detected on the D channel, the physical layer device negates
L1GRA. The MPC823 then stops its transmission and retransmits the frame when L1GRA
is reasserted. This procedure is handled automatically for the first two buffers of a frame.
For the primary rate IDL, the MPC823 supports up to four 8-bit channels in the frame,
determined by the serial interface RAM programming. Additionally, the MPC823 can be
used to assert strobes to support additional external IDL channels. The IDL interface
supports the CCITT I.460 recommendation for data rate adaptation since it separately
accesses each bit of the IDL bus. The current-route RAM specifies the bits that are
supported by the IDL interface and the serial controller. The receiver only receives the bits
that are enabled by the receiver route RAM. Otherwise, the transmitter only transmits the
bits that are enabled by the transmitter route RAM and three-states the L1TXD A pin.
16.7.6.2 PROGRAMMING THE IDL INTERFACE. You can program the channels used for
the IDL bus interface to the appropriate configuration. First, using the GM A bit, program the
SIMODE register to the IDL grant mode for that channel. If the receive and transmit section
are used for interfacing to the same IDL bus, using the CRT A bits you can internally connect
the receive clock and sync signals to the serial interface RAM transmit section. However,
the RAM section used for the IDL channels must be programmed to the preferred routing.
For more information, see Section 16.7.5 Serial Interface Programming Model .
You must now define the IDL frame structure to be a 1-bit delay from frame sync to data, to
falling edge sample sync, and the clock edge to transmit on the rising edge of the clock.
Program the L1TXD A pin to be three-stated when inactive by using the parallel I/O
open-drain register. To support the D channel, you must program the appropriate GM A bit
in the SIMODE register and program the RAM entry to route data to that serial
communication controller. The two definitions of IDL—8 and 10 bits—are only supported by
modifying the serial interface RAM programming. In both cases, the L1GRA pin is sampled
with the L1TSYNC A signal and transferred to the D channel serial communication controller
as a grant indication. The same procedure is used to support an IDL bus in the second
channel.
MPC823 REFERENCE MANUAL
16-145
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