mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 367

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Bits 26–30—Reserved
These bits are reserved and must be set to 0.
V—Valid
This bit indicates that the contents of the base and option registers are valid. The CSx signal
does not assert until this bit is set. An access to a region that does not have this bit set can
cause a bus monitor timeout. After a system reset, the value of this bit in BR0 depends on
the BDIS bit value in the hard reset configuration word, which is described in
Section 4.3.1.1 Hard Reset Configuration Word.
15.3.1.2 OPTION REGISTERS. The option registers (OR0-7) contain the address mask
and address type mask bit for address bus comparison. It also includes the CS general field
and all the GPCM parameters. After reset, OR0 is referred to as the Boot OR0 and it has a
special functionality until the first write to OR0.
BOOT OR0
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
0 = This bank is invalid.
1 = This bank is valid.
16
AM
0
0
R
17
1
ATM
18
2
R
0
Freescale Semiconductor, Inc.
For More Information On This Product,
19
3
CSNT/
SAM
20
MPC823 REFERENCE MANUAL
4
R
1
Go to: www.freescale.com
ACS/G5LA,G5LS
21
5
11
R
22
6
(IMMR & 0xFFFF0000) + 0x104
(IMMR & 0xFFFF0000) + 0x106
23
BIH
7
R
1
AM
R
0
24
8
25
9
SCY
1
R
10
26
11
27
SETA
12
28
0
R
Memory Controller
TRLX
13
29
R
1
EHTR
14
30
R
0
15-11
RES
15
31
R
0