mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 889

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

• MRBLR—The serial peripheral interface has one maximum receive buffer length entry
Bits 0–2—Reserved
These bits are reserved and must be set to 0.
BO—Byte Ordering
You must set these bits to select the required byte ordering of the data buffer. If this bit
AT—Address Type 1–3
These bits contain the function code value used during the SDMA channel memory
to define its receive buffer length and it defines the maximum number of bytes that the
MPC823 writes to a receive buffer on the serial peripheral interface before moving to
the next buffer. The MPC823 can write fewer bytes to the buffer than the MRBLR value
if an error or end-of-frame occurs, but it never writes more bytes than the MRBLR value.
Buffers you supply for the MPC823 to use must always be at least as long as MRBLR.
The transmit buffers for a serial peripheral interface are not affected by the value you
program into MRBLR and they can have different lengths, as needed. You can choose
the number of bytes to be transmitted by programming the DATA LENGTH field in the
TX buffer descriptor.
field is modified on-the-fly, it takes effect at the beginning of the next frame or at the
beginning of the next buffer descriptor.
access. AT0 is driven with a 1 to identify this SDMA channel access as a DMA-type
access.
00 = The DEC/Intel convention is used for byte ordering (swapped operation) and
01 = PowerPC little-endian byte ordering. As data is transmitted onto the serial line
1X = Motorola byte ordering (normal operation) is also called big-endian byte
is also called little-endian byte ordering. The transmission order of bytes within
a buffer word is reversed in comparison to the Motorola mode. This mode is
supported only for 32-bit port size memory.
from the data buffer, the least-significant byte of the buffer double-word
contains data to be transmitted earlier than the most-significant byte of the
same buffer double-word.
ordering. As data is transmitted onto the serial line from the data buffer, the
most-significant byte of the buffer word contains data to be transmitted earlier
than the least-significant byte of the same buffer word.
Note:
management controller is operating. However, if it is modified in a single bus
cycle with one 16-bit move (not two 8-bit bus cycles back-to-back), then a
dynamic change in the receive buffer length can be successfully achieved. This
occurs when the communication processor module transfers control to the next
RX buffer descriptor in the table. Thus, a change to MRBLR does not have an
immediate effect. To guarantee that the change occurs on a particular RX buffer
descriptor, you must only change the MRBLR while the SMCx receiver is
disabled. The value of MRBLR must be greater than zero and it must be even if
the character length of the data is greater than 8 bits.
The MRBLR is not intended to be dynamically changed while a serial
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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