mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1065

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Development Capabilities and Interface
Greater-than-or-equal-to and less-than-or-equal-to are easily obtained from these four
conditions. Refer to Section 20.3.1.5 Generating Compare Types for more information.
Using the AND-OR logic structures “in range” and “out of range”, detections of address and
data comparators are supported. Using the counters, you can program a breakpoint to be
recognized after an event has been detected after a predefined number of times.
The L-data comparators operate on load or store fixed-point data. When operating on
fixed-point data, the L-data comparators perform a comparison on bytes, half-words, and
words. They treat numbers as either signed or unsigned values. The comparators generate
match events and then instruction match events enter the instruction AND-OR logic where
the instruction watchpoints and breakpoint are generated. The asserted instruction
watchpoints can generate the instruction breakpoint. Two different events can decrement
one of the counters. When a counter on one of the instruction watchpoints expires, the
instruction breakpoint is asserted.
DEVELOPMENT
WATCHPOINTS
DEVELOPMENT
PERIPHERALS
SYSTEM OR
EXTERNAL
INTERNAL
LCTRL2
LOGIC
PORT
MSR
Figure 20-1. Watchpoint and Breakpoint Support in the Core
SOFTWARE TRAP ENABLE BITS
WATCHPOINTS
MASKABLE BREAKPOINT
NONMASKABLE BREAKPOINT
DEVELOPMENT PORT TRAP ENABLE BITS
NONMASKED CONTROL BIT
MSR
RI
Freescale Semiconductor, Inc.
For More Information On This Product,
PERIPHERALS
DEVELOPMENT
CPM CODE
ACCESSIBLE
INTERNAL
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
X
COUNTERS
X
X
X
BIT WISE AND
BIT WISE OR
WATCHPOINT
BREAKPOINT
MOTOROLA
TO CPU
PINS
TO

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