mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 786

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.9.23 Programming the SCCx Ethernet Controller
16.9.23.1 SCCx ETHERNET MODE REGISTER. When a serial communication controller
is in Ethernet mode, the 16-bit, memory-mapped, read/write protocol-specific mode register
is referred to as the SCCx Ethernet mode register (PSMR–SCC Ethernet). Since each
protocol has specific requirements, the PSMR bits are different for each implementation.
HBC—Heartbeat Checking
FC—Force Collision
RSH—Receive Short Frames
PSMR–SCC ETHERNET
RESET
• Non-Octet Error (Dribbling Bits) — The SCCx Ethernet controller handles up to seven
• CRC Error—When a CRC error occurs, the channel closes the buffer, sets the CR bit
FIELD
ADDR
R/W
BIT
dribbling bits when the receive frame terminates nonoctet aligned and it checks the
CRC of the frame on the last octet boundary. If there is a CRC error, then the frame
nonoctet aligned error is reported, the RXF bit is set, and the alignment error counter is
incremented. If there is no CRC error, then no error is reported.
in the RX buffer descriptor, and the RXF bit in the SCCE–Ethernet register. The channel
also increments the CRC error counter (CRCEC). After receiving a frame with a CRC
error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC
error can be ignored if checking is not required.
0 = No heartbeat checking is performed. Do not wait for a collision after transmission.
1 = Wait 20 transmit clocks or 2 s for a collision asserted by the transceiver after
0 = Normal operation.
1 = The channel forces a collision when each frame is transmitted. The MPC823 must
0 = Discard short frames that are not as long as MINFLR.
1 = Receive short frames.
transmission. The HB bit in the TX buffer descriptor is set if the heartbeat is not
heard within 20 transmit clocks.
be configured in loopback operation when using this feature so that you can test
the collision logic. In the end, the retry limit for each transmit frame is exceeded.
HBC
R/W
0
0
R/W
FC
1
0
RSH
R/W
2
0
Freescale Semiconductor, Inc.
R/W
IAM
For More Information On This Product,
3
0
MPC823 REFERENCE MANUAL
4
CRC
R/W
0
Go to: www.freescale.com
5
(IMMR & 0xFFFF0000) + 0xA28
PRO BRO SBT
R/W
6
0
R/W
7
0
R/W
8
0
LPB
R/W
9
0
RES LCW
R/W
10
0
R/W
11
0
12
R/W
NIB
13
0
MOTOROLA
14
FDE
R/W
15
0