mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 698

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
W—Wrap (Final Buffer Descriptor in Table)
I—Interrupt
L—Last
TC—TX CRC
This bit is valid only when the L bit is set. Otherwise, it is ignored.
CM—Continuous Mode
UN—Underrun
This bit indicates when the SCCx HDLC controller encounters a transmitter underrun
condition while transmitting the associated data buffer. The SCCx HDLC controller writes
these bits after it finishes transmitting the associated data buffer.
CT—CTS Lost
This bit indicates when CTSx in NMSI mode or layer 1 grant is lost in GCI mode during frame
transmission. If data from more than one buffer is currently in the FIFO when this error
occurs, this bit is set in the currently open TX buffer descriptor. The SCCx HDLC controller
writes these bits after it finishes transmitting the associated data buffer.
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer
0 = No interrupt is generated after this buffer is serviced.
1 = The TXB or TXE bit in the SCCE–HDLC register is set when this buffer is serviced
0 = This is not the last buffer in the frame.
1 = This is the last buffer in the frame.
0 = Transmit the closing flag after the last data byte. This setting can be used to send
1 = Transmit the CRC sequence after the last data byte.
0 = Normal operation.
1 = The R bit is not cleared by the communication processor module after this buffer
has been used, the communication processor module transmits data from the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table are programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
by the SCCx HDLC controller. These bits can cause interrupts if they are enabled.
a bad CRC after the data for testing purposes.
descriptor is closed, thus allowing the associated data buffer to be automatically
retransmitted next time the communication processor module accesses this buffer
descriptor. However, the R bit is cleared if an error occurs during transmission,
regardless of how the CM bit is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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