mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1117

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
IEEE 1149.1 Test Access Port
The MPC823 implementation includes a TAP controller, a 4-bit instruction register, and two
test registers (a 1-bit bypass register and a 397-bit boundary scan register). An overview of
the MPC823 scan chain implementation is illustrated in the figure below. The TAP controller
consists of the following signals:
• TCK—A test clock input to synchronize the test logic.
• TMS—A test mode select input (with an internal pull-up resistor) that is sampled on the
• TDI—A test data input (with an internal pull-up resistor) that is sampled on the rising
• TDO—A three-stateable test data output that is actively driven in the shift-IR and
• TRST—An asynchronous reset with an internal pull-up resistor that provides TAP
rising edge of TCK to sequence the TAP controller’s state machine.
edge of TCK.
shift-DR controller states. TDO changes on the falling edge of TCK.
controller initialization and other logic required by the standard. For normal operation of
the MPC823, this signal pin must make a level transition to low before initialization
begins. Typically, if the TAP is used, connect the TRST signal to the PORESET through
a diode (cathode to PORESET).
TRST
TDI
TMS
TCK
Freescale Semiconductor, Inc.
Figure 21-1. Test Logic Block Diagram
For More Information On This Product,
INSTRUCTION APPLY & DECODE REGISTER
MPC823 REFERENCE MANUAL
3
BYPASS
4-BIT INSTRUCTION REGISTER
TAP CONTROLLER
BOUNDARY SCAN REGISTER
Go to: www.freescale.com
2
1
0
M
U
X
M
U
X
MOTOROLA
TDO

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