mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 873

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.11.7.15 SMC1 TRANSPARENT TSA PROGRAMMING EXAMPLE. The following is
an example initialization sequence for the SMC1 transparent channel over the time-slot
assigner. It is assumed that the time-slot assigner and TDM pins have already been set up
to route time-slot data to the SMC1 transmitter and receiver. Refer to Section 16.7 The
Serial Interface with Time-Slot Assigner for examples of how to configure the time-slot
assigner. The transmit and receive clocks and synchronization signals are provided
internally from the time-slot assigner.
10. Initialize the TX buffer descriptor and assume the TX data buffer is at 0x00002000 in
11. Write 0xFF to the SMCE–Transparent register to clear any previous events.
12. Write 0x13 to the SMCM–Transparent register to enable all possible serial
13. Write 0x00000010 to the CIMR to allow SMC1 to generate a system interrupt. The
14. Write 0x3830 to the SMCMR to configure 8-bit characters, unreversed data, and
15. Write 0x3833 to the SMCMR to enable the SMCx transmitter and receiver. This
1. Write RBASE and TBASE in the SMC1 parameter RAM to point to the RX buffer
2. Program the CPCR to execute the INIT TX AND RX PARAMS command. Write
3. Write 0x0001 to the SDCR to initialize the SDMA configuration register.
4. Write 0x18 to RFCR and TFCR for normal operation.
5. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16
6. Initialize the RX buffer descriptor and assume the RX data buffer is at 0x00001000 in
main memory and contains five 8-bit characters. Write 0xB000 to TX_BD_Status,
0x0005 to TX_BD_Length, and 0x00002000 to TX_BD_Pointer.
management controller interrupts.
CICR must also be initialized.
normal operation (not loopback). Notice that the transmitter and receiver have not
been enabled yet.
additional write ensures that the TEN and REN bits are enabled last.
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of the dual-port RAM and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
0x0091 to the CPCR.
bytes, so MRBLR = 0x0010.
main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional),
and 0x00001000 to RX_BD_Pointer.
Note: After 5 bytes are transmitted, the TX buffer descriptor is closed and after 16 bytes
are received the receive buffer is closed too. Any data received after 16 bytes
causes a busy (out-of-buffers) condition since only one RX buffer descriptor is
prepared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
Communication Processor Module
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