mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 208

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

10.3.3.1 DATA CACHE CONTROL AND STATUS REGISTER. The data cache control
and status register (DC_CST) is used to configure and access the status of the data cache.
DEN—Data Cache Enable Status
This read-only bit indicates the status of the data cache. Any attempt to write to it is ignored.
You can enable or disable the data cache by writing to the CMD field.
DFWT—Data Cache Force Writethrough
This bit is read-only and any attempt to write to it is ignored. Write to the CMD field to set or
force writethrough mode.
LES—Little-Endian Swap
This bit is read-only. Write to the CMD field to set or clear little-endian swap mode. Refer to
Section 14 Endian Modes for details about using this bit to achieve the required endian
behavior.
DC_CST
NOTE: — = Undefined.
RESET
RESET
FIELD
FIELD
SPR
SPR
R/W
R/W
BIT
BIT
0 = Data cache is disabled.
1 = Data cache is enabled.
0 = Data cache mode is determined by the memory management unit.
1 = Data cache is forced writethrough.
0 = Address of the data and the instruction caches is the unchanged address from the
1 = Address munging performed by the core is reversed before accessing the data
core. No byte swap is done on the data and instruction caches’ external accesses.
cache, the instruction cache and storage. Byte swap is performed for the
instruction and data caches’ external accesses. This bit is a read-only bit and any
attempt to write to it is ignored.
DEN
16
0
0
R
DFWT
17
1
R
0
LES
18
2
R
0
Freescale Semiconductor, Inc.
For More Information On This Product,
RES
R/W
19
3
0
20
MPC823 REFERENCE MANUAL
4
Go to: www.freescale.com
21
5
CMD
R/W
0
22
6
23
7
RESERVED
R/W
568
568
0
24
8
RESERVED
R/W
0
25
9
CCER1
10
26
0
R
CCER2
11
27
0
R
CCER3
12
28
0
R
13
29
RESERVED
Data Cache
R/W
14
30
0
10-5
15
31