mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1091

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Development Capabilities and Interface
The watchpoint trap enable and VSYNC functions are described in
Section 20.3 Generating Watchpoints And Breakpoints and Section 20.2 Program
Flow Tracking. The DEBUG PORT command allows the development tool to either assert
or negate breakpoint requests, reset the processor, or activate or deactivate the fast
download procedure. Status out of the development interface port in the trap enable mode
is shown in Table 20-10.
START MODE CONTROL
START
1
1
MODE
1
Table 20-9. DEBUG PORT Command Shifted Into the DPS Register
1
Table 20-8. Trap Enable Data Shifted Into DPS Register
CONTROL
0
1
INSTRUCTION WATCHPOINT
FIRST
Freescale Semiconductor, Inc.
For More Information On This Product,
TRAP ENABLES
EXTENDED
x
0
1
1
x
x
x
0
1
OPCODE
SECOND
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
x
x
0
1
x
0
1
x
x
THIRD
MAJOR OPCODE
00100 — 11110
0 = Disabled
1 = Enabled
FOURTH
00000
00001
00010
00011
00011
00011
11111
11111
11111
11111
DATA WATCHPOINT
TRAP ENABLES
FIRST
SECOND VSYNC
Negate Nonmaskable Breakpoint
Assert Nonmaskable Breakpoint
Negate Maskable Breakpoint
Assert Maskable Breakpoint
Start Download Procedure
End Download Procedure
Hard Reset Request
Soft Reset Request
FUNCTION
Reserved
Reserved
NOP
Trap Enable Control
Transfer Data to
FUNCTION
Register
MOTOROLA