mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1134

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

21.3 THE INSTRUCTION REGISTER
The MPC823 JTAG implementation includes the public instructions—extest, sample/
preload, bypass, and clamp. One additional public instruction—hi-z—is capable of
disabling all device output drivers. The MPC823 includes a 4-bit instruction register that
consists of a shift register with four parallel outputs. Data is transferred from the shift register
to the parallel outputs during the update-IR controller state. The four bits are used to decode
the five unique instructions listed in Table 21-2.
The parallel output of the instruction register is reset to all ones in the test-logic-reset
controller state. Notice that this preset state is equivalent to the bypass instruction. During
the capture-IR controller state, the parallel inputs to the instruction shift register are loaded
with the clamp command code.
21.3.1 The External Test Instruction
The external test (extest) instruction selects the 397-bit boundary scan register and asserts
an internal reset for the MPC823 system logic to force a known beginning internal state while
performing external boundary scan operations. By using the TAP controller, the register is
capable of scanning user-defined values into the output buffers, capturing values presented
to the input pins, and controlling the output drive of three-stateable output or bidirectional
pins. For more details on the function and use of extest, refer to the IEEE 1149.1 standard.
NOTE:
B3
0
0
0
0
B0 (LSB) is shifted first.
Freescale Semiconductor, Inc.
For More Information On This Product,
B2
X
Table 21-2. Instruction Decoding
0
0
1
1
CODE
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
B1
0
0
1
0
0
B0
X
0
1
0
1
CLAMP and BYPASS
SAMPLE/PRELOAD
INSTRUCTION
BYPASS
EXTEST
HI-Z
IEEE 1149.1 Test Access Port
21-19