mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 959

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

16.15.5.4 CPM INTERRUPT IN-SERVICE REGISTER. Each bit in the 32-bit read/write
CPM interrupt in-service register (CISR) corresponds to a CPM interrupt source. In a
vectored interrupt environment, the CPM interrupt controller sets the CISR bit when the core
acknowledges the interrupt by setting the IACK bit in the CPM interrupt vector register. Your
interrupt service routine must clear this bit after servicing is complete. If an event register
exists for this peripheral, its bits would normally be cleared as well. To clear a bit in the CISR,
write a 1 to that bit. Since you can only clear bits in this register, bits written as zeros will not
be affected. The CISR is cleared by reset.
You can read this register to determine the interrupt requests that are currently in progress
for each CPM interrupt source. More than one bit in the CISR can be a 1 if higher priority
CPM interrupts are allowed to interrupt lower priority level interrupts within the same CPM
interrupt level. For example, the TIMER1 interrupt routine could interrupt the handling of the
TIMER2 routine using a special nesting technique described earlier. During this time, you
can see both the TIMER2 and the TIMER1 bits simultaneously set in the CISR.
CISR
RESET
RESET
FIELD
ADDR
FIELD
ADDR
R/W
R/W
BIT
BIT
PC15
PC11
R/W
R/W
16
0
0
0
Note: The USB or SCCx CIMR bit positions are unaffected by the relative priority
PC10
USB
R/W
R/W
17
1
0
0
between the USB or SCCs. To clear bits that were set by multiple interrupt events,
you must clear all the unmasked events in the corresponding event register. If a
bit in the CIMR is masked at the same time that the corresponding CIPR bit
causes an interrupt request to the core, then the interrupt is not processed, but
the error vector is issued if the interrupt acknowledge cycle occurs with no other
CPM interrupts pending. Thus, you must always include an error vector routine,
even if it just contains the rfi instruction. The error vector cannot be masked.
SCC2
RES
R/W
R/W
18
2
0
0
Freescale Semiconductor, Inc.
TIMER
SCC3
For More Information On This Product,
R/W
R/W
19
3
0
3
0
RES
R/W
PC9
R/W
20
MPC823 REFERENCE MANUAL
4
0
0
Go to: www.freescale.com
PC14
R/W
PC8
R/W
21
5
0
0
TIMER
R/W
PC7
R/W
22
6
1
0
0
(IMMR & 0xFFFF0000) + 0x94C
(IMMR & 0xFFFF0000) + 0x94E
PC13
RES
R/W
R/W
23
7
0
0
TIMER
PC12
R/W
R/W
24
8
0
4
0
SDMA
R/W
PC6
R/W
25
9
0
0
Communication Processor Module
IDMA1
R/W
R/W
10
26
SPI
0
0
IDMA2
SMC1
R/W
R/W
11
27
0
0
SMC2
RES
R/W
R/W
12
28
0
0
TIMER
R/W
PC5
R/W
13
29
2
0
0
R–TT
R/W
PC4
R/W
14
30
0
0
16-507
RES
R/W
R/W
15
31
I2C
0
0