mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 143

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

6.3.7 The External Interrupt
The core provides one external interrupt line: the architectural maskable external interrupt.
In the MPC823, this interrupt is generated by the on-chip interrupt controller. It is software
acknowledged and maskable by the MSR
hardware to disable external interrupts when any interrupt is taken.
6.3.7.1 LATENCY
When an external interrupt is detected, every instruction that can retire from the history
buffer does so and the interrupt is assigned to the instruction at the head of the history buffer
(at point B in Table 6-4). However, the following conditions must be met before the
instruction at the head of the queue can retire.
Any instruction that does not meet these criteria is discarded with all of its side effects and
the execution at the end of the interrupt handler resumes with the first instruction that was
discarded. If all the instructions in the history buffer were allowed to complete, execution at
the end of the interrupt handler resumes with the next instruction. External interrupt latency
depends on the time required to reference memory. The measurement is equal to the time
taken for one of the following three possible events, in addition to the interval from B to E as
shown in Table 6-4.
Actual system-level interrupt latency can be worse than just the interval from B to E. If the
instruction prior to the one in which the interrupt was assigned generates an exception, then
the exception is recognized first. If minimal interrupt latency is an important system
parameter, interrupt handlers must save the machine context and reenable external
interrupt as rapidly as possible so that a pending external interrupt receives service quickly.
• The instruction must be completed without exception
• The instruction must either be a mtspr , mtmsr , or rfi instruction, a memory reference,
or a storage or cache control instruction.
Longest load/store multiple/string instruction used
or
One bus cycle for aligned access
or
Two bus cycles for unaligned access
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
EE
bit, which is automatically cleared by the
The PowerPC Core
6-13