mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 554

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Communication Processor Module
16.6.3.11 IDMA OPERAND TRANSFERS. Once IDMA successfully arbitrates for the bus,
it can begin making operand transfers. The source IDMA bus cycle has timing identical to
an internal master read bus cycle. The destination IDMA bus cycle’s timing is controlled by
the memory controller and is therefore identical to any other internal access. The
two-channel IDMA controller supports dual-address transfers and single address transfers,
but only channel 1 supports single-buffer (single-address burst fly-by) transfers. The
dual-address operand transfer consists of a source operand read and a destination operand
write. Each single-address operand transfer consists of one external bus cycle that allows a
read or write cycle to occur. A single-buffer mode transfer is exactly like the single-address
operand transfer, except it is an external burst transfer.
16.6.3.11.1 Transfer Identification. The following are ways to externally determine if
IDMA is executing a bus cycle:
16.6.3.11.2 Dual-Address Mode. The two IDMA channels can be programmed to operate
in a dual-address transfer mode in which the operand is read from the source address
specified by the pointer and placed in internal storage. The operand read can take several
bus cycles to complete because of differences in source and destination operand sizes.
Once it is read, the operand is then written to the address specified in the destination
address pointer. This transfer may also be several bus cycles long. You can use a variety
of peripheral, memory, and operand size combinations in a dual-address mode transfer.
There are two types of dual-address mode cycles:
• Monitor the AT signals or SDMA channels to determine if they have the unique function
• Monitor the SDACKx signal, which shows accesses to the peripheral device. SDACKx
• Dual-address source read—Initially, the IDMA controller copies the source data buffer
• Dual-address destination write—Initially, the IDMA controller copies the destination
code that identifies an IDMA transfer.
activates on either the source or destination bus cycles, depending on the TYPE field
of the DCMR.
pointer buffer descriptor into the SAPR field of the parameter RAM. During this type of
IDMA cycle, the SDBP is used to drive the address bus, the SFCR is used to drive the
source address type, and the DCMR is used to drive the size control. Data is read from
the memory or peripheral and placed in the internal storage when the bus cycle is
terminated. When the complete operand has been read, the SAPR is incremented by
1, 2, 4, or 16, depending on the address and size information specified by the IDMA
channel mode register (DCMR).
data buffer pointer buffer descriptor into the DAPR field of the parameter RAM. During
this type of IDMA cycle, the data in the internal storage is written to the device or
memory selected by the AT field in the DAPR, the AT field in the DFCR, and the SIZE
field in the DCMR. The same options exist for operand size and alignment in this cycle
as they did in the dual address source read cycle. When the complete operand is
written, the DAPR is incremented by 1, 2, 4, or 16 according to the DCMR and the
D_BYTE_C is decremented by the number of bytes transferred. If it is equal to zero and
the transfer is completed with no errors, the DONE bit in the IDSRx is set. Refer to
Section 16.6.3.2 IDMA Parameter RAM Memory Map for more information.
Freescale Semiconductor, Inc.
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