mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 63

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

SPKROUT
SIGNAL
RETRY
D[0:31]
IRQ2
IRQ4
IRQ3
IRQ4
TEA
RSV
DP0
DP1
KR
TA
BI
PIN NUMBER
See Table 2-2
breakout.
for pin
A12
C11
B12
D9
B7
C3
D4
Table 2-1. Signal Descriptions (Continued)
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Transfer Acknowledge—This bidirectional three-state signal indicates that the
slave device addressed in the current transaction has accepted the data transferred
by the master (write) or has driven the data bus with valid data (read). The signal
behaves as an output when the PCMCIA memory controller takes control of the
transaction. The only exception occurs when the memory controller is controlling the
slave access by means of the GPCM and the corresponding option register is
instructed to wait for an external assertion of the transfer acknowledge line. Every
slave device should negate the ta signal after the end of the transaction and
immediately three-state it to avoid contentions on the line if a new transfer is initiated
addressing other slave devices. A pull-up resistor should be connected to this signal
to keep a master device from detecting the assertion of this signal when no slave is
addressed in a transfer or when the address detection for the addressed slave is
slow.
Transfer Error Acknowledge —This open-drain signal indicates that a bus error
occurred in the current transaction. It is driven asserted by the MPC823 when the bus
monitor does not detect a bus cycle termination within a reasonable amount of time.
The assertion of TEA causes the termination of the current bus cycle, thus ignoring
the state of TA.
Burst Inhibit—This bidirectional three-state signal indicates that the slave device
addressed in the current burst transaction is unable to support burst transfers. The
signal behaves as an output when the PCMCIA memory controller takes control of
the transaction. When the MPC823 drives out the signal for a specific transaction, it
asserts or negates BI during the transaction according to the value you specify in the
appropriate control registers. It negates the signal after the end of the transaction
and immediately three-states it to avoid contentions if a new transfer is initiated
addressing other slave devices.
Reservation—This three-state signal is output by the MPC823 in conjunction with
the address bus to indicate that the internal core initiated a transfer as a result of a
stwcx or lwarx instruction.
Interrupt Request 2—This input is one of the eight external signals that can request
(by means of the internal interrupt controller) a service routine from the core.
Interrupt Request 4—This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
It should be noted that the interrupt request signal that is sent to the interrupt
controller is the logical AND of this signal (if defined to function as IRQ4) and the
DP1/IRQ4 (if defined to function as IRQ4).
Kill Reservation —This input is used as a part of the storage reservation protocol
when the MPC823 initiated a transaction as the result of a stwcx instruction.
Retry— This input is used by the slave device to indicate that it is unable to accept
the transaction. The MPC823 has to relinquish the ownership of the bus and initiate
the transaction again after winning again in the bus arbitration.
Speaker Out —This output signal is used to provide a digital audio waveform to be
driven to the system’s speaker.
Data Bus —This bidirectional three-state signal provides the general-purpose data
path between the MPC823 and all other devices. Although the data path is a
maximum of 32 bits wide, it can be dynamically sized to support 8-, 16-, or 32-bit
transfers. D0 is the most-significant bit of the data bus.
Data Parity 0—This bidirectional three-state signal provides parity generation and
checking for the data bus lane D[0:7] by transferring to a slave device initiated by the
MPC823. The parity function can be defined independently for each one of the
addressed memory banks (if controlled by the memory controller) and for the rest of
the slaves on the external bus.
Interrupt Request 3 —This input signal is one of the eight external signals that can
request (by means of the internal interrupt controller) a service routine from the core.
Data Parity 1 —This bidirectional three-state signal provides parity generation and
checking for the data bus lane D[8:15] by transferring to a slave device initiated by
the MPC823. The parity function can be defined independently for each one of the
addressed memory banks (if controlled by the memory controller) and for the rest of
the slaves on the external bus.
Interrupt Request 4 —This input is one of the eight external lines that can request
(by means of the internal interrupt controller) a service routine from the core. It should
be noted that the interrupt request signal that is sent to the interrupt controller is the
logical AND of this signal (if defined to function as IRQ4) and the KR/SPKROUT/
IRQ4 if defined to function as IRQ4.
MPC823 REFERENCE MANUAL
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DESCRIPTION
External Signals
2-3