mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 197

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Instruction Cache
Some commands may take some time to generate errors. In the current implementation,
LOAD & LOCK is the only command to which this applies. Therefore, when executing these
commands, you must insert an isync instruction immediately after the instruction cache
command and check the error status in the IC_CST after the isync. The error type bits in
the IC_CST are sticky, thus allowing you to perform a series of instruction cache commands
before checking the termination status. These bits are set by the hardware and cleared by
the software.
Only commands that are not immediately executed need to be followed by an isync
instruction for the hardware to perform them correctly. However, all commands need to be
followed by an isync to make sure all instruction fetches that are after the instruction cache
commands in the program stream are affected by the instruction cache command. When the
instruction cache is executing a command it is busy, so it stops any treatment of core
requests. This eventually results in a machine stall.
9.4.1 Invalidating the Instruction Cache
The MPC823 implements the PowerPC instruction cache block invalidate ( icbi ) instruction
if it only pertains to the MPC823 instruction cache. This instruction does not broadcast on
the external bus and the MPC823 does not snoop this instruction if it is broadcasted by other
masters. This command is not privileged and has no associated error cases. The instruction
cache performs this instruction in one clock cycle. To accurately calculate the latency of this
instruction, bus latency must be taken into consideration.
The invalidate all instruction cache operation is privileged and any attempt to perform it
when the core is in the problem state (MSR
=1) results in a program interrupt. When it is
PR
invoked and MSR
= 0, all valid lines in the cache, except the lines that are locked, are
PR
made invalid. As a result of this command, the lines’ LRU points to an unlocked Way or to
Way 0 if all of the lines are unlocked. This last feature is useful when initializing the
instruction cache out of reset. For more information, refer to Section 9.8 Reset Sequence .
To invalidate the whole cache, set the INVALIDATE ALL command in the IC_CST. This
command has no associated error cases. The instruction cache performs this instruction in
one clock cycle. To accurately calculate the latency of this instruction, bus latency must be
taken into consideration.
MPC823 REFERENCE MANUAL
9-9
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