mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 1155

• Manufacturer Part Number: mpc823rg
• Description: Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
• Manufacturer: Freescale Semiconductor, Inc

MPC823 Instruction Set
B.3 INSTRUCTION FIELDS
The table below shows the instruction fields used in the various instruction formats.
MB (21–25) and
CRM (12–19)
crbA (11–15)
crbB (16–20)
IMM (16–19)
OPCD (0–5)
frC (21–25)
ME (26–30)
BD (16–29)
NB (16–20)
r A (11–15)
r B (16–20)
BI (11–15)
BO (6–10)
frD (6–10)
frS (6–10)
d (16–31)
r D (6–10)
r S (6–10)
LI (6–29)
OE (21)
LK (31)
Rc (31)
AA (30)
FIELD
Absolute address bit.
0
1
Immediate field specifying a 14-bit signed two's complement branch displacement that is
concatenated on the right with 0b00 and sign-extended to 32 bits.
This field is used to specify a bit in the CR to be used as the condition of a branch conditional
instruction.
This field is used to specify options for the branch conditional instructions.
This field is used to specify a bit in the CR to be used as a source.
This field is used to specify a bit in the CR to be used as a source.
This field mask is used to identify the CR fields that are to be updated by the mtcrf instruction.
Immediate field specifying a 16-bit signed two's complement integer that is sign-extended to 32 bits.
NOT USED BY MPC823.
NOT USED BY MPC823.
NOT USED BY MPC823.
NOT USED BY MPC823.
Immediate field specifying a 24-bit signed two's complement integer that is concatenated on the
right with 0b00 and sign-extended to 32 bits.
Link bit.
0
1
These fields are used in rotate instructions to specify a 32 bit mask.
This field is used to specify the number of bytes to move in an immediate string load or store.
This field is used for extended arithmetic to enable setting OV and SO in the XER.
Primary opcode field
This field is used to specify a GPR to be used as a source or destination.
This field is used to specify a GPR to be used as a source.
Record bit.
0
1
Exceptions are referred to as interrupts in the architecture specification.)
This field is used to specify a GPR to be used as a destination.
This field is used to specify a GPR to be used as a source.
The immediate field represents an address relative to the current instruction address (CIA).
The immediate field represents an absolute address. The effective address (EA) of the branch
Does not update the link register (LR).
Updates the LR. If the instruction is a branch instruction, the address of the instruction
following the branch instruction is placed into the LR.
Does not update the condition register (CR).
Updates the CR to reflect the result of the operation.
For integer instructions, CR bits 0–2 are set to reflect the result as a signed quantity and CR
bit 3 receives a copy of the summary overflow bit, XER[SO]. The result as an unsigned quantity
or a bit string can be deduced from the EQ bit.
The effective (logical) address of the branch is either the sum of the LI field sign-extended to
32 bits and the address of the branch instruction or the sum of the BD field sign-extended to
32 bits and the address of the branch instruction.
is the LI field sign-extended to 32 bits or the BD field sign-extended to 32 bits. The LI and LD
fields are sign-extended to 32.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
DESCRIPTION
MOTOROLA