mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 922

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Communication Processor Module
DATA LENGTH
This field represents the number of octets the communication processor module must
transmit from this buffer descriptor data buffer. However, it is never modified by the
communication processor module. Normally, this value must be greater than zero. The I
controller writes these bits after it finishes transmitting the associated data buffer.
TX DATA BUFFER POINTER
This field always points to the first location of the associated data buffer. They can be even
or odd, unless the number of actual data bits in the character is greater than 8 bits, in which
case the transmit buffer pointer must be even. The buffer can reside in internal or external
memory. The I
buffer.
16.13.7.4 I
(I2ADD) register holds the address for this I
are operating in multimaster, slave, or local loopback mode. You must clear this register
before using I
match the address of an external device, thus causing incorrect behavior.
SAD— Slave Address 0–6
This field holds the slave address for the I
Bit 7—Reserved
This bit is reserved and must be set to 0.
I2ADD
NOTE:
RESET
FIELD
ADDR
R/W
BIT
= Undefined.
2
C ADDRESS REGISTER. The 8-bit, memory-mapped, read/write I
0
2
2
C Master Mode. If you do not, this register may cause the I
C controller writes these bits after it finishes transmitting the associated data
Freescale Semiconductor, Inc.
1
For More Information On This Product,
MPC823 REFERENCE MANUAL
2
Go to: www.freescale.com
(IMMR & 0xFFFF0000) + 0x864
2
C port.
SAD
R/W
2
3
C port. You must program this register if you
4
5
2
C controller to
6
2
C address
MOTOROLA
RESERVED
R/W
7
2
C

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