mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 309

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mpc823rg

Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
13.2.1 Control Signals
The MPC823 initiates a bus cycle by driving the address, size, address type, cycle type, and
read/write outputs. At the beginning of a bus cycle, the TSIZ0 and TSIZ1 signals are driven
with the AT signals. TSIZx indicates the number of bytes to be transferred during an operand
cycle that consists of one or more bus cycles. These signals are valid at the rising edge of
the clock in which the TS signal is asserted. The RD/WR signal determines the direction of
the transfer during a bus cycle. Driven at the beginning of a bus cycle, RD/WR is valid at the
rising edge of the clock in which the TS signal is asserted. However, RD/WR only transitions
when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for
consecutive write cycles.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 13-2. MPC823 Bus Signals
MPC823 REFERENCE MANUAL
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1
2
4
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1
1
1
1
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4
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A[6:31]
RD / WR
BURST
TSIZ[0:1]
AT[0:3]
PTR
RSV
STS
BDIP
TS
KR/RETRY
D[0:31]
DP[0:3]
BI
TA
TEA
BR
BG
BB
RESERVATION
TERMINATION
ATTRIBUTES
PROTOCOL
TRANSFER
TRANSFER
TRANSFER
ADDRESS
ARBITRATION
START
CYCLE
DATA
AND
External Bus Interface
13-3

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