h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 125

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

5.7.2
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Instructions that Disable Interrupts
When Interrupts Are Disabled
Figure 5.6 Conflict between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
Rev. 3.00 Oct 04, 2005 page 85 of 598
TCIV exception handling
Section 5 Interrupt Controller
REJ09B0155-0300