h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 19

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 8-Bit Timers
11.1 Features............................................................................................................................. 251
11.2 Input/Output Pins.............................................................................................................. 253
11.3 Register Descriptions........................................................................................................ 253
11.4 Operation .......................................................................................................................... 262
11.5 Operation Timing.............................................................................................................. 263
11.6 Operation with Cascaded Connection............................................................................... 267
11.7 Interrupt Sources............................................................................................................... 268
11.8 Usage Notes ...................................................................................................................... 269
10.9.7 Conflict between Buffer Register Write and Compare Match............................. 245
10.9.8 Conflict between TGR Read and Input Capture .................................................. 246
10.9.9 Conflict between TGR Write and Input Capture ................................................. 247
10.9.10 Conflict between Buffer Register Write and Input Capture................................. 248
10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................ 249
10.9.12 Conflict between TCNT Write and Overflow/Underflow ................................... 250
10.9.13 Multiplexing of I/O Pins...................................................................................... 250
10.9.14 Interrupts in Module Stop Mode.......................................................................... 250
11.3.1 Timer Counters (TCNT) ...................................................................................... 254
11.3.2 Time Constant Registers A (TCORA)................................................................. 254
11.3.3 Time Constant Registers B (TCORB) ................................................................. 254
11.3.4 Timer Control Registers (TCR) ........................................................................... 255
11.3.5 Timer Control/Status Registers (TCSR) .............................................................. 257
11.4.1 Pulse Output ........................................................................................................ 262
11.5.1 TCNT Incrementation Timing ............................................................................. 263
11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs ............. 264
11.5.3 Timing of Timer Output When a Compare-Match Occurs.................................. 264
11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs .................... 265
11.5.5 TCNT External Reset Timing.............................................................................. 265
11.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 266
11.6.1 16-Bit Count Mode .............................................................................................. 267
11.6.2 Compare-Match Count Mode .............................................................................. 267
11.7.1 Interrupt Sources and DTC Activation ................................................................ 268
11.7.2 A/D Converter Activation.................................................................................... 268
11.8.1 Conflict between TCNT Write and Clear ............................................................ 269
11.8.2 Conflict between TCNT Write and Increment..................................................... 270
11.8.3 Conflict between TCOR Write and Compare-Match........................................... 271
11.8.4 Conflict between Compare-Matches A and B ..................................................... 271
11.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 272
11.8.6 Conflict between Interrupts and Module Stop Mode........................................... 273
11.8.7 Notes on Cascaded Connection ........................................................................... 273
..................................................................................................... 251
Rev. 3.00 Oct 04, 2005 page xix of xl