h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 487

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h8s-2628

Manufacturer Part Number
h8s-2628
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 16 Synchronous Serial Communication Unit (SSU)
SCS
(Hi-Z)
MSS
Transfer enabled
internal signal
Transfer
CE
end
Conflict error detection period
Figure 16.11 Conflict Error Detection Timing (After Transfer End)
16.5
Interrupt Requests
The SSU interrupt requests consist of transmit data register empty, transmit end, receive data
register full, overrun error, and conflict error. Of these interrupt sources, transmit data register
empty, transmit end, receive data register full can activate the DTC for data transfer.
The TDRE, TEND, and RDRF bits are automatically cleared to 0 by the DTC data transfer. Since
these interrupt requests are allocated to four vector addresses: SSEr_i0, SSRx_i0, SSTx_i0 and
SSERT_i1, the interrupt sources must be distinguished by flags. Table 16.2 lists interrupt sources.
Rev. 3.00 Oct 04, 2005 page 447 of 598
REJ09B0155-0300

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