h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 549

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

21.4
21.4.1
A transition is made to software standby mode if the SLEEP instruction is executed when the
SBYCR SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator,
all stop. However, the contents of the CPU’s internal registers, on-chip RAM data, and the states
of on-chip peripheral modules other than the SCI, SSU, HCAN, A/D converter, and the states of
I/O ports, are retained. In this mode, the oscillator stops, and therefore power consumption is
significantly reduced.
21.4.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins
means of the
Exiting Sleep Mode by
When the
Clearing with an interrupt
When an NMI or IRQ5 to IRQ0 interrupt request signal is input, clock oscillation starts, and
after the time set in bits STS2 to STS0 in SBYCR has elapsed, stable clocks are supplied to the
entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ5 to IRQ0 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ5 to IRQ0
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
Clearing with the
When the
oscillation starts, clocks are supplied to the entire chip. Note that the
until clock oscillation settles. When the
handling.
Clearing with the
When the
Software Standby Mode
Transition to Software Standby Mode
Clearing Software Standby Mode
R E S
S T B Y
R E S
S T B Y
pin or
pin is driven low, clock oscillation is started. At the same time as clock
pin level is driven low, a transition is made to hardware standby mode.
pin is driven low, a transition is made to hardware standby mode.
R E S
S T B Y
S T B Y
pin
S T B Y
pin
pin.
Pin:
R E S
pin goes high, the CPU begins reset exception
Rev. 3.00 Oct 04, 2005 page 509 of 598
Section 21 Power-Down Modes
R E S
I R Q 5
pin must be held low
REJ09B0155-0300
to
I R Q 0
) , or by