h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 392

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 14 Serial Communication Interface (SCI)
14.6.4
Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization synchronous with a synchronous clock input or output,
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.19 shows a sample flow
chart for serial data reception.
Rev. 3.00 Oct 04, 2005 page 352 of 598
REJ09B0155-0300
Synchronization
clock
Serial data
RDRF
ORER
starts receiving data, and stores the received data in RSR.
in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has finished.
Serial Data Reception (Clocked Synchronous Mode)
RXI interrupt
request
generated
Figure 14.18 Example of SCI Operation in Reception
Bit 7
Bit 0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
1 frame
Bit 7
Bit 0
RXI interrupt
request generated
Bit 1
ERI interrupt request
generated by overrun
error
Bit 6
Bit 7