h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 139

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

7.2
The Bus Controller has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
control the bus.
7.2.1
Each bus master requests the bus mastership by means of a bus request signal. The bus arbiter
detects the bus masters’ bus request signals, and if the bus mastership is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is cancelled.
The order of priority of the bus mastership is as follows:
7.2.2
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus mastership and is currently operating, the bus mastership is not
necessarily transferred immediately. The CPU is the lowest-priority bus master, and if a bus
request is received from the DTC, the bus arbiter transfers the bus mastership to the bus master
that issued the request. The timing for transfer of the bus mastership is as follows:
The DTC can release the bus mastership after a vector read, a register information read (3 states),
a single data transfer, or a register information write (3 states). It does not release the bus
mastership during a register information read (3 states), a single data transfer, or a register
information write (3 states).
The bus mastership is transferred at a break between bus cycles.
However, if a bus cycle is executed in discrete operations, as in the case of a longword-size
access, the bus mastership is not transferred between such operations. For details, refer to
section 2.7, Bus Status in Instruction Execution in the H8S/2600 Series, H8S/2000 Series
Programming Manual.
If the CPU is in sleep mode, it transfers the bus mastership immediately.
Bus Arbitration
Order of Priority of the Bus Masters
(High)
Bus Transfer Timing
DTC
>
CPU
(Low)
Rev. 3.00 Oct 04, 2005 page 99 of 598
Section 7 Bus Controller
REJ09B0155-0300