h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 8

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Rev. 3.00 Oct 04, 2005 page viii of xl
Item
15.3.16 Unread
Message Status
Register (UMSR)
15.3.18 Message
Control (MC15 to
MC0)
15.4.2 Initialization
after Hardware Reset
Figure 15.8 Detailed
Description of One Bit
Table 15.3 Setting
Range for TSEG1 and
TSEG2 in BCR
15.8.10 HCAN TXCR
Operation
15.8.12 Canceling
HCAN Reset and
HCAN Sleep Mode
Section 16
Synchronous Serial
Communication Unit
(SSU)
16.3.6 SS transmit
Data Register 3 to 0
(SSTDR3 to SSTDR0)
Page
393
397
403
404
420
421
423
433
Revision (See Manual for Details)
Description amended
(Before) [Setting condition]
before RXPR is cleared
[Clearing condition]
The received message has been overwritten by a new message
before being read.
(After) The received message has been overwritten by a new
message before being read.
[ Setting condition]
RXPR is cleared
[Clearing condition]
Description amended
Data Length Code
(Before) 1000: 8 bytes … 1111: 8 bytes
Figure 15.8 amended
Note * amended
Note: * Settable when bits BRP is not B 000000
Description amended
Conditions:
Countermeasures:
Countermeasure:
Description amended
... reset for HCAN or HCAN sleep mode (MCR0 = 0 or MCR5 =
0), confirm that …
Description deleted
... different clock polarity and clock phase. Figure 16.1 is a …
Description amended
… SSTDR0 are valid. Do not attempt to access invalid SS
transmit data registers. When the SSU detects …
1 time quanta
SYNC_SEG
The HRxD pin is stacked to 1 because of …
1-bit time (25 to 8 time quanta)
PRSEG
A transmit wait message must be …
When a new message is received before
Transmission must not be canceled …
Time segment 1 (TSEG1)
Writing 1
Writing 1
4 to 16 time quanta
When a new message is received
PHSEG1
(After) 1***: 8 bytes
2 to 8 time quanta
Time segment 2
(TSEG2)
PHSEG2