h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 474

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 Synchronous Serial Communication Unit (SSU)
16.3.7
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR3 to SSRDR0 are valid. Do
not attempt to access invalid SS receive data registers.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is receive-enabled. Since SSTRSR and SSRDR
function as a double buffer in this way, continuous receive operations can be performed. Read
SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR cannot be written to by
the CPU. The initial value of this register is H'00.
16.3.8
SSTRSR is a shift register that transmits and receives serial data.
When data from SSTDR to SSTRSR is transferred with MLS 0, bit 0 of transmit data is bit 0 in
the SSTDR contents (LSB first communication). When data from SSTDR to SSTRSR is
transferred with MLS 1, bit 0 of transmit data is bit 7 in the SSTDR contents (MSB first
communication). To perform serial data transmission, the SSU transfers data starting from LSB
(bit 0) in SSTRSR to the SSO pin.
In reception, the SSU sets serial data that has been input from the SSI pin to SSTRSR starting
from LSB (bit 0) and converts it into parallel data. When 1-byte data has been received, the
SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed
by the CPU.
Rev. 3.00 Oct 04, 2005 page 434 of 598
REJ09B0155-0300
SS Receive Data Register 3 to 0 (SSRDR3 to SSRDR0)
SS Shift Register (SSTRSR)