h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 28

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 PC Break Controller (PBC)
Figure 6.1
Figure 6.2
Section 7 Bus Controller
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Section 8 Data Transfer Controller (DTC)
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 8.11
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10 Example of Synchronous Operation Setting Procedure....................................... 211
Figure 10.11 Example of Synchronous Operation .................................................................... 212
Figure 10.12 Compare Match Buffer Operation ....................................................................... 213
Figure 10.13 Input Capture Buffer Operation........................................................................... 213
Figure 10.14 Example of Buffer Operation Setting Procedure ................................................. 214
Figure 10.15 Example of Buffer Operation (1)......................................................................... 215
Figure 10.16 Example of Buffer Operation (2)......................................................................... 216
Rev. 3.00 Oct 04, 2005 page xxviii of xl
Block Diagram of PC Break Controller............................................................... 88
Operation in Power-Down Mode Transitions...................................................... 92
On-Chip Memory Access Cycle .......................................................................... 95
On-Chip Support Module Access Cycle.............................................................. 96
On-Chip HCAN Module Access Cycle (with Wait States) ................................. 97
On-Chip SSU Module Access Cycle ................................................................... 98
Block Diagram of DTC ....................................................................................... 102
Block Diagram of DTC Activation Source Control............................................. 108
Location of DTC Register Information in Address Space ................................... 109
Flowchart of DTC Operation............................................................................... 112
Memory Mapping in Normal Mode..................................................................... 113
Memory Mapping in Repeat Mode...................................................................... 114
Memory Mapping in Block Transfer Mode......................................................... 116
Chain Transfer Operation .................................................................................... 117
DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ 118
DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) ........................................................................................... 119
DTC Operation Timing (Example of Chain Transfer)......................................... 119
Block Diagram of TPU........................................................................................ 170
Example of Counter Operation Setting Procedure............................................... 205
Free-Running Counter Operation ........................................................................ 206
Periodic Counter Operation ................................................................................. 207
Example of Setting Procedure for Waveform Output by Compare Match .......... 207
Example of 0 Output/1 Output Operation............................................................ 208
Example of Toggle Output Operation.................................................................. 208
Example of Input Capture Operation Setting Procedure...................................... 209
Example of Input Capture Operation................................................................... 210