h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 339

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

13.2.3
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized
to H'1F by a reset signal from the
overflows.
Note:
Bit
7
6
5
4 to
0
Bit Name
WOVF
RSTE
RSTS
*
Reset Control/Status Register (RSTCSR)
Only 0 can be written, for flag clearing.
Initial Value
0
0
0
All 1
R E S
R/W
R/(W) *
R/W
R/W
pin, and not by the WDT internal reset signal caused by
Description
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
[Clearing condition]
Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reset Select
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
Reserved
These bits are always read as 1 and cannot be
modified.
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
Set when TCNT overflows (changed from
H'FF to H'00) in watchdog timer mode
Cleared by reading RSTCSR when WOVF =
1, and then writing 0 to WOVF
Rev. 3.00 Oct 04, 2005 page 299 of 598
Section 13 Watchdog Timer
REJ09B0155-0300