h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 478

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 Synchronous Serial Communication Unit (SSU)
Data Transmission
Figure 16.5 shows an example of transmission operation, and figure 16.6 shows an example of
data transmission flowchart.
When transmitting data, the SSU operates as shown below.
In master device mode, the SSU outputs a transfer clock and data. In slave device mode, when a
low level signal is input to the
pin and a transfer clock is input to the SSCK pin, the SSU
S C S
outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after initialization of the SSU automatically clears the TDRE bit
in SSSR to 0, and the contents of SSTDR is transferred to SSTRSR. After that, the SSU sets the
TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI
interrupt is generated.
When 1-frame data has been transferred with the TDRE bit cleared to 0, the SSTDR contents are
transferred to SSTRSR to start the next transmission. When the 8th bit of transmit data has been
transferred with the TDRE bit set to 1, the TEND bit in SSSR is set to 1 and the state is retained.
At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output
level of the SSCK pin is fixed at a high level when CPOS 0 and at a low level when CPOS 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
Rev. 3.00 Oct 04, 2005 page 438 of 598
REJ09B0155-0300