h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 29

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 10.17 Cascaded Operation Setting Procedure................................................................ 217
Figure 10.18 Example of Cascaded Operation (1) .................................................................... 218
Figure 10.19 Example of Cascaded Operation (2) .................................................................... 218
Figure 10.20 Example of PWM Mode Setting Procedure......................................................... 221
Figure 10.21 Example of PWM Mode Operation (1) ............................................................... 221
Figure 10.22 Example of PWM Mode Operation (2) ............................................................... 222
Figure 10.23 Example of PWM Mode Operation (3) ............................................................... 223
Figure 10.24 Example of Phase Counting Mode Setting Procedure ......................................... 224
Figure 10.25 Example of Phase Counting Mode 1 Operation................................................... 225
Figure 10.26 Example of Phase Counting Mode 2 Operation................................................... 226
Figure 10.27 Example of Phase Counting Mode 3 Operation................................................... 227
Figure 10.28 Example of Phase Counting Mode 4 Operation................................................... 228
Figure 10.29 Phase Counting Mode Application Example ....................................................... 230
Figure 10.30 Count Timing in Internal Clock Operation .......................................................... 234
Figure 10.31 Count Timing in External Clock Operation......................................................... 234
Figure 10.32 Output Compare Output Timing.......................................................................... 235
Figure 10.33 Input Capture Input Signal Timing ...................................................................... 235
Figure 10.34 Counter Clear Timing (Compare Match)............................................................. 236
Figure 10.35 Counter Clear Timing (Input Capture) ................................................................ 236
Figure 10.36 Buffer Operation Timing (Compare Match)........................................................ 237
Figure 10.37 Buffer Operation Timing (Input Capture)............................................................ 237
Figure 10.38 TGI Interrupt Timing (Compare Match).............................................................. 238
Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................. 238
Figure 10.40 TCIV Interrupt Setting Timing ............................................................................ 239
Figure 10.41 TCIU Interrupt Setting Timing ............................................................................ 239
Figure 10.42 Timing for Status Flag Clearing by CPU............................................................. 240
Figure 10.43 Timing for Status Flag Clearing by DTC Activation........................................... 240
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 241
Figure 10.45 Conflict between TCNT Write and Clear Operations.......................................... 242
Figure 10.46 Conflict between TCNT Write and Increment Operations .................................. 243
Figure 10.47 Conflict between TGR Write and Compare Match ............................................. 244
Figure 10.48 Conflict between Buffer Register Write and Compare Match............................. 245
Figure 10.49 Conflict between TGR Read and Input Capture .................................................. 246
Figure 10.50 Conflict between TGR Write and Input Capture ................................................. 247
Figure 10.51 Conflict between Buffer Register Write and Input Capture................................. 248
Figure 10.52 Conflict between Overflow and Counter Clearing............................................... 249
Figure 10.53 Conflict between TCNT Write and Overflow...................................................... 250
Section 11 8-Bit Timers
Figure 11.1
Figure 11.2
Block Diagram of 8-Bit Timer Module ............................................................... 252
Example of Pulse Output ..................................................................................... 262
Rev. 3.00 Oct 04, 2005 page xxix of xl