h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 518

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 19 ROM
19.6.1
Table 19.4 shows the boot mode operations from a reset end to a branch to the programming
control program.
1. In boot mode, the flash memory programming control program must be prepared in the host
2. SCI_2 should be set to asynchronous mode with the transfer format of 8-bit data, 1 stop bit,
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
4. When the bit rate matching is completed, the chip transmits 1-byte data H'00 to the host to
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800
6. Before branching to the programming control program, the chip terminates transfer operations
7. Boot mode can be cleared by a reset. End the reset by driving the reset pin low, waiting at least
8. Do not change the MD pin input level in boot mode.
Rev. 3.00 Oct 04, 2005 page 478 of 598
REJ09B0155-0300
beforehand. Prepare a programming control program in accordance with the description in
section 19.8, Flash Memory Programming/Erasing.
and no parity.
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI_2 bit rate to match
that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit 1-byte data H'55 to the chip. If
reception could not be performed normally, initiate boot mode again by a reset. Depending on
the host’s transfer bit rate and system clock frequency of this LSI, there will be a discrepancy
between the bit rates of the host and the chip. To operate the SCI properly, set the host’s
transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19.5.
to H'FFEFBF is used to store the programming control program to be transferred from the
host. The boot program area cannot be used until the execution is shifted to the programming
control program.
by SCI_2 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value is
retained in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. At this time, the TxD pin is in the high level output
state. The contents of the CPU general registers are undefined immediately after branching to
the programming control program. These registers must be initialized at the beginning of the
programming control program, since the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT
overflow occurs.
Boot Mode