h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 15

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

5.7
Section 6 PC Break Controller (PBC)
6.1
6.2
6.3
6.4
Section 7 Bus Controller
7.1
7.2
5.6.4
5.6.5
Usage Notes ...................................................................................................................... 84
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
Features............................................................................................................................. 87
Register Descriptions........................................................................................................ 88
6.2.1
6.2.2
6.2.3
6.2.4
Operation .......................................................................................................................... 90
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Usage Notes ...................................................................................................................... 93
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
Basic Timing..................................................................................................................... 95
7.1.1
7.1.2
7.1.3
7.1.4
Bus Arbitration ................................................................................................................. 99
Break Control Register A (BCRA) ...................................................................... 89
Break Control Register B (BCRB) ...................................................................... 90
I Bit Set by LDC, ANDC, ORC, or XORC Instruction ....................................... 93
Interrupt Response Times .................................................................................... 83
DTC Activation by Interrupt................................................................................ 84
Conflict between Interrupt Generation and Disabling ......................................... 84
Instructions that Disable Interrupts...................................................................... 85
When Interrupts Are Disabled ............................................................................. 85
Interrupts during Execution of EEPMOV Instruction ......................................... 86
IRQ Interrupt ....................................................................................................... 86
Break Address Register A (BARA) ..................................................................... 88
Break Address Register B (BARB) ..................................................................... 89
PC Break Interrupt Due to Instruction Fetch ....................................................... 90
PC Break Interrupt Due to Data Access .............................................................. 91
PC Break Operation at Consecutive Data Transfer ............................................. 91
Operation in Transitions to Power-Down Modes ................................................ 91
When Instruction Execution Is Delayed by One State......................................... 92
Module Stop Mode Setting .................................................................................. 93
PC Break Interrupts ............................................................................................. 93
CMFA and CMFB ............................................................................................... 93
PC Break Interrupt when DTC Is Bus Master ..................................................... 93
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, or RTS Instruction....................................................................... 93
PC Break Set for Instruction Fetch at Address Following Bcc Instruction.......... 94
PC Break Set for Instruction Fetch at Branch Destination Address of Bcc
Instruction............................................................................................................ 94
On-Chip Memory Access Timing (ROM, RAM)................................................ 95
On-Chip Support Module Access Timing ........................................................... 96
On-Chip HCAN Module Access Timing............................................................. 97
On-Chip SSU Module and Realtime Input Port Data Register Access Timing ... 98
................................................................................................... 95
........................................................................... 87
Rev. 3.00 Oct 04, 2005 page xv of xl