h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 131

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.2
1. Set the break address in BARA.
2. Set the break conditions in BCRA.
3. After execution of the instruction that performs a data access on the set address, a PC break
4. After priority determination by the interrupt controller, PC break interrupt exception handling
6.3.3
6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address
space address as the break address. Stack operations and branch address reads are included in
data accesses.
Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 5 to 3
(BAMA2 to BAMA0). Set bits 2 and 1 (CSELA1 and CSELA0) to 01, 10, or 11 to specify
data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
request is generated and the condition match flag (CMFA) is set.
is started.
When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
When a PC break interrupt is generated at a DTC transfer address
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
sleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break
exception handling is executed. After execution of PC break exception handling, the
instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).
When the SLEEP instruction causes a transition to software standby mode:
After execution of the SLEEP instruction, a transition is made to software standby mode, and
PC break exception handling is not executed. However, the CMFA or CMFB flag is set (figure
6.2 (B)).
Operation in Transitions to Power-Down Modes
PC Break Interrupt Due to Data Access
PC Break Operation at Consecutive Data Transfer
Rev. 3.00 Oct 04, 2005 page 91 of 598
Section 6 PC Break Controller (PBC)
REJ09B0155-0300