h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 447

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

transmission abort acknowledge interrupts can be generated for individual mailboxes in the
mailbox interrupt mask register (MBIMR).
Arbitration Field Setting: The arbitration field is set by the message control registers MCx[8] to
MCx[5] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the
RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28
to ID-0) and the RTR bit are set, and the IDE bit is set to 1.
Control Field Setting: In the control field, the byte length of the data to be transmitted is set
within the range of zero to eight bytes. The register to be set is the message control register
MCx[1] in a transmit mailbox.
Data Field Setting: In the data field, the data to be transmitted is set within the range zero to
eight. The registers to be set are the message data registers MDx[8] to MDx[1]. The byte length of
the data to be transmitted is determined by the data length code in the control field. Even if data
exceeding the value set in the control field is set in the data field, up to the byte length set in the
control field will actually be transmitted.
Message Transmission: If the corresponding mailbox transmit wait bit (TXPR15 to TXPR1) in
the transmit wait register (TXPR) is set to 1 after message control and message data registers have
been set, the message enters transmit wait state. If the message is transmitted error-free, the
corresponding acknowledge bit (TXACK15 to TXACK1) in the transmit acknowledge register
(TXACK) is set to 1, and the corresponding transmit wait bit (TXPR15 to TXPR1) in the transmit
wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to
MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit
(IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts,
interrupts may be sent to the CPU.
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
Message Transmission Cancellation: Transmission cancellation can be specified for a message
stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the
bit for the corresponding mailbox (TXCR15 to TXCR1) to 1 in the transmit cancel register
(TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When
cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the
corresponding bit is set to 1 in the abort acknowledge register (ABACK), and then an interrupt to
the CPU can be requested. Also, if the corresponding bit (MBIMR15 to MBIMR1) in the mailbox
CAN bus arbitration failure (failure to acquire the bus)
Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)
Section 15 Controller Area Network (HCAN)
Rev. 3.00 Oct 04, 2005 page 407 of 598
REJ09B0155-0300