h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 145

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

8.2.2
MRB is an 8-bit register that selects the DTC operating mode.
8.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
8.2.5
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
Bit
7
6
5 to 0
Bit Name
CHNE
DISEL
DTC Destination Address Register (DAR)
DTC Transfer Count Register A (CRA)
DTC Mode Register B (MRB)
DTC Source Address Register (SAR)
Initial Value
Undefined
Undefined
Undefined
R/W
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to 8.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the interrupt source flag, and clearing of DTCER,
are not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after the end of a data transfer.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
Reserved
These bits have no effect on DTC operation. Only 0
should be written to these bits.
Section 8 Data Transfer Controller (DTC)
Rev. 3.00 Oct 04, 2005 page 105 of 598
REJ09B0155-0300