h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 78

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
Table 2.10 Block Data Transfer Instructions
2.6.2
The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
Figure 2.11 shows examples of instruction formats.
Rev. 3.00 Oct 04, 2005 page 38 of 598
REJ09B0155-0300
Instruction
EEPMOV.B
EEPMOV.W
Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Condition Field
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
Size
Function
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
if R4L
else next;
if R4
else next;
Repeat @ER5+
Until R4L = 0
Repeat @ER5+
Until R4 = 0
R4L–1
R4–1
0 then
0 then
R4
R4L
@ER6+
@ER6+