h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 548

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h8s-2628

Manufacturer Part Number
h8s-2628
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 21 Power-Down Modes
When the
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the
Figure 21.2 shows the timing for transition to and clearance of medium-speed mode.
21.3
21.3.1
If SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode.
In sleep mode, CPU operation stops, however the contents of the CPU’s internal registers are
retained. Other peripheral modules do not stop.
21.3.2
Sleep mode is cleared by any interrupt, or signals at the
Rev. 3.00 Oct 04, 2005 page 508 of 598
REJ09B0155-0300
Exiting Sleep Mode by Interrupts:
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or if interrupts other than NMI are masked by the
CPU.
Exiting Sleep Mode by
Setting the
driving the
peripheral module clock
Bus master clock
Internal address bus
Internal write signal
,
Sleep Mode
Transition to Sleep Mode
Clearing Sleep Mode
R E S
S T B Y
Figure 21.2 Medium-Speed Mode Transition and Clearance Timing
R E S
R E S
pin is set low and medium-speed mode is cancelled, operation shifts to the reset
pin is driven low, a transition is made to hardware standby mode.
pin low level selects the reset state. After the stipulated reset input duration,
pin high level restart the CPU performing reset exception processing.
R E S
SCKCR
pin:
Medium-speed mode
R E S
, or
S T B Y
SCKCR
pins.

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