h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 443

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quanta (tq).
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, BSP, and
SJW) are shown in table 15.2.
Table 15.2 Limits for the Settable Value
Notes: 1. SJW is stipulated in the CAN specifications:
Name
Time segment 1
Time segment 2
Baud rate prescaler
Bit sample point
Re-synchronization jump width
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
3
TSEG2
TSEG1 > TSEG2
SJW
1 time quanta
SYNC_SEG
SJW
0
Figure 15.8 Detailed Description of One Bit
1-bit time (25 to 8 time quanta)
PRSEG
Time segment 1 (TSEG1)
4 to 16 time quanta
Abbreviation
TSEG1
TSEG2
BRP
BSP
SJW *
1
Section 15 Controller Area Network (HCAN)
PHSEG1
Rev. 3.00 Oct 04, 2005 page 403 of 598
Min. Value
B'0011 *
B'001 *
B'000000
B'0
B'00
2 to 8 time quanta
Time segment 2
3
2
(TSEG2)
PHSEG2
REJ09B0155-0300
Max. Value
B'1111
B'111
B'111111
B'1
B'11