h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 307

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

11.6
If bits CKS2 to CKS0 in one of TCR_1 and TCR_0, or TCR_3 and TCR_2 are set to B'100, the 8-
bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be
used (16-bit timer mode) or compare-matches of 8-bit channel 0 (Channel 2) can be counted by
the timer of channel 1 (Channel 3) (compare-match count mode). In the case that channel 0 is
connected to channel 1 in cascade, the timer operates as described below.
11.6.1
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
11.6.2
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare-match A for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
Setting of compare-match flags
Counter clear specification
Pin output
The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT_1 and TCNT_0 together) is cleared when a 16-bit compare-
match occurs. The 16-bit counter (TCNT_1 and TCNT_0 together) is cleared even if
counter clear by the TMRI01 pin has also been set.
The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot
be cleared independently.
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with
the 16-bit compare-match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with
the lower 8-bit compare-match conditions.
Operation with Cascaded Connection
16-Bit Count Mode
Compare-Match Count Mode
Rev. 3.00 Oct 04, 2005 page 267 of 598
Section 11 8-Bit Timers
REJ09B0155-0300