h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 160

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h8s-2628

Manufacturer Part Number
h8s-2628
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 8 Data Transfer Controller (DTC)
Table 8.5
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 8.6
Note:
The number of execution states is calculated from using the formula below. Note that
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 3.00 Oct 04, 2005 page 120 of 598
REJ09B0155-0300
Mode
Normal
Repeat
Block transfer
Bus width
Access states
Execution
status
Object to be Accessed
*
Number of execution states = I · (1 S
Not available in this LSI.
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
Register Information
Read/Write
J
6
6
6
S
S
S
S
S
S
S
I
J
K
K
L
L
M
Chip
RAM
On-
32
1
1
1
1
1
1
ROM
Chip
On-
I
16
)
1
1
1
1
1
1
(J · S
On-Chip I/O
Registers
8
2
2
4
2
4
Data Read
K
1
1
N
J
K · S
16
2
2
2
2
2
K
1
+ L · S
Data Write
L
1
1
N
2
4
2
4
2
4
External Devices *
8
L
6+2m
6+2m
6+2m
)
3+m
3+m
3
M · S
Internal
Operations
M
3
3
3
M
2
2
2
2
2
2
is the sum
16
3+m
3+m
3+m
3+m
3+m
3

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