h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 431

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

15.3.13 Interrupt Mask Register (IMR)
IMR is a 16-bit register containing flags that enable or disable requests by individual interrupt
sources. The reset interrupt flag cannot be masked.
Bit
15
14
13
12
11
10
9
8
Bit Name
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1
Initial Value
1
1
1
1
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Overload Frame Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR7 (OVR0) is enabled. When set to 1, it is
masked.
Bus Off Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR6 (ERS0) is enabled. When set to 1, it is
masked.
Error Passive Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR5 (ERS0) is enabled. When set to 1, it is
masked.
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR4 (OVR0) is enabled. When set to 1, it is
masked.
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR3 (OVR0) is enabled. When set to 1, it is
masked.
Remote Frame Request Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR2 (OVR0) is enabled. When set to 1, it is
masked.
Receive Message Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR1 (RM1) is enabled. When set to 1, it is
masked.
Reserved
This bit is always read as 0. The write value should
always be 0.
Section 15 Controller Area Network (HCAN)
Rev. 3.00 Oct 04, 2005 page 391 of 598
REJ09B0155-0300