h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 340

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 Watchdog Timer
13.3
13.3.1
To use the WDT as a watchdog timer, set the WT/
must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system malfunction or other
error, the WOVF bit in RSTCSR is set to 1. If the RSTE bit in RSTCSR is set to 1, an internal
reset is issued. This is shown in figure 13.2. At this time, select the power-on reset by clearing the
RSTS bit in RSTCSR to 0. The internal reset signal is output for 518 states.
If a reset caused by a signal input to the
WDT overflow, the reset by the
0.
13.3.2
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
Rev. 3.00 Oct 04, 2005 page 300 of 598
REJ09B0155-0300
Watchdog Timer Mode Operation
Interval Timer Mode
Operation
Legend:
WT/IT:
TME:
Note: * The internal reset signal is generated only if the RSTE bit is set to 1.
Internal reset signal *
Timer mode select bit
Timer enable bit
Figure 13.2 Example of WDT0 Watchdog Timer Operation
H'FF
H'00
TCNT value
WT/IT=1
TME=1
R E S
Write H'00
to TCNT
pin has priority and the WOVF bit in RSTCSR is cleared to
R E S
pin occurs at the same time as a reset caused by a
internal reset is
generated
I T
bit in TCSR and the TME bit to 1. Software
Overflow
WOVF=1
518 states
WT/IT=1
TME=1
Write H'00
to TCNT
Time