h8s-2628 Renesas Electronics Corporation., h8s-2628 Datasheet - Page 71

• Manufacturer Part Number: h8s-2628
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Table 2.4
Note:
Instruction
DIVXS
CMP
NEG
EXTU
EXTS
TAS *
MAC
CLRMAC
LDMAC
STMAC
2
1. Refers to the operand size.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
B:
W: Word
L:
Arithmetic Operations Instructions (2)
Byte
Longword
Size *
B/W
B/W/L
B/W/L
W/L
W/L
B
L
1
Function
Rd ÷ Rs
Performs signed division on data in two general registers: either 16 bits ÷
8 bits
quotient and 16-bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
0 – Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
Rd (zero extension)
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
Rd (sign extension)
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
@ERd – 0, 1
Tests memory contents, and sets the most significant bit (bit 7) to 1.
(EAs)
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits
16 bits
0
Clears the multiply-accumulate register to zero.
Rs
Transfers data between a general register and a multiply-accumulate
register.
MAC
MAC, MAC
(EAd) + MAC
8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
16 bits + 32 bits
16 bits + 42 bits
Rd
Rd
(<bit 7> of @ERd)
Rd
Rd
Rd
MAC
32 bits, saturating
42 bits, non-saturating
Rev. 3.00 Oct 04, 2005 page 31 of 598
REJ09B0155-0300
Section 2 CPU
16-bit