IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 112

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–28
Figure 5–28. Sequencing of FPGA Configuration and PCIe Link Initialization in Stratix V Devices
Figure 5–29. 100 ms Requirement
Note to
(1) The ability for Gen2-capable designs to begin link initialization and ultimately to reach L0 before the FPGA is configured is pending device
PCI Express Compiler User Guide
PCIe_LinkTraining_Enumeration
PCIe_LinkTraining_Enumeration
characterization.
PLD_Fabric_Programming
Figure
pld_clk_in_use
5–29:
IO_POF_Load
pld_clk_ready
IO_POF_Load
dl_ltssm[4:0]
perst_n
Figure 5–28
bring up the PCI Express link.
As
1. Initialize the I/O ring and PCI Express hard IP core.
2. Initialize the PCI Express link.
3. Configure the FPGA fabric which can be performed using CvPCIe.
4. After the PLD clock is ready, the PCI Express IP core asserts pld_clk_in_use to
Figure 5–29
state.
For additional information about reset in Stratix V devices refer to
Devices” on page
Figure 5–28
indicate that it is operating in user mode.
(Note 1)
illustrates the sequencing for the processes that configure the FPGA and
illustrates the timing relationship between perst_n and the LTSSM L0s
illustrates, configuration includes the following steps:
7–4.
detect detect.active polling.active
100 ms
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
“Reset in Stratix V
Avalon-ST Interface
L0