IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 273

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–40. ebfm_display Procedure
Table 15–41. ebfm_log_stop_sim Procedure
Table 15–42. ebfm_log_set_suppressed_msg_mask Procedure
December 2010 Altera Corporation
Location
Syntax
Argument
Return
Location
Syntax
Argument success
Return
Location
Syntax
Argument
altpcietb_bfm_log.v or altpcietb_bfm_log.vhd
VHDL: ebfm_log_stop_sim(success)
Verilog VHDL: return:=ebfm_log_stop_sim(success);
Always 0
altpcietb_bfm_log.v or altpcietb_bfm_log.vhd
bfm_log_set_suppressed_msg_mask (msg_mask)
msg_mask
altpcietb_bfm_log.v or altpcietb_bfm_log.vhd
VHDL: ebfm_display(msg_type, message)
Verilog HDL: dummy_return:=ebfm_display(msg_type, message);
msg_type
message
always 0
■
ebfm_log_stop_sim VHDL Procedure or Verilog HDL Function
The ebfm_log_stop_sim procedure stops the simulation.
ebfm_log_set_suppressed_msg_mask Procedure
The ebfm_log_set_suppressed_msg_mask procedure controls which message types
are suppressed.
When ebfm_log_set_stop_on_msg_mask is called, the simulation can be stopped
after the message is displayed, based on the value of the bit mask.
Message type for the message. Should be one of the constants defined in
page
In VHDL, this argument is VHDL type string and contains the message text to be displayed.
In Verilog HDL, the message string is limited to a maximum of 100 characters. Also, because
Verilog HDL does not allow variable length strings, this routine strips off leading characters of
8’h00 before displaying the message.
Applies only to the Verilog HDL routine.
When set to a 1, this process stops the simulation with a message indicating successful
completion. The message is prefixed with SUCCESS:.
Otherwise, this process stops the simulation with a message indicating unsuccessful
completion. The message is prefixed with FAILURE:.
This value applies only to the Verilog HDL function.
In VHDL, this argument is a subtype of std_logic_vector, EBFM_MSG_MASK. This vector
has a range from EBFM_MSG_ERROR_CONTINUE downto EBFM_MSG_DEBUG.
In Verilog HDL, this argument is reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG].
In both languages, a 1 in a specific bit position of the msg_mask causes messages of the type
corresponding to the bit position to be suppressed.
15–44.
PCI Express Compiler User Guide
Table 15–39 on
15–45