IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 38

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–12
Constrain the Design
Table 2–6. Automatically Generated Constraints Files
PCI Express Compiler User Guide
Constraint Type
General
Timing
Directory
<working_dir><variation>.tcl (top.tcl)
<working_dir><variation>.sdc (top.sdc)
The Quartus project directory for the chaining DMA design example is in
<working_dir>\top_examples\chaining_dma\. Before compiling the design using
the Quartus II software, you must apply appropriate design constraints, such as
timing constraints. The Quartus II software automatically generates the constraint
files when you generate the PCI Express IP core.
Table 2–6
If you want to do an initial compilation to check any potential issues without creating
pin assignments for a specific board, you can do so after running the following two
steps that constrain the chaining DMA design example:
1. To apply Quartus II constraint files, type the following commands at the Tcl
2. To add the Synopsys timing constraints to your design, complete the following
console command prompt:
source ../../top.tcl r
1
steps:
a. On the Assignments menu, click Settings.
b. Under Timing Analysis Settings, click TimeQuest Timing Analyzer.
c. Under SDC files to include in the project, click add. Browse to your
<working_dir> to add top.sdc.
describes these constraint files.
To display the Quartus II Tcl Console, on the View menu, point to Utility
Windows and click Tcl Console.
This file includes various Quartus II constraints. In
particular, it includes virtual pin assignments. Virtual
pin assignments allow you to avoid making specific
pin assignments for top-level signals while you are
simulating and not yet ready to map the design to
hardware.
This file is the Synopsys Design Constraints File (.sdc)
which includes timing constraints.
Description
December 2010 Altera Corporation
Chapter 2: Getting Started
Constrain the Design