IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 354

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Info–2
PCI Express Compiler User Guide
July 2010
July 2010
Date
Version
10.0
10.0
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Added support for Stratix V GX and GT devices.
Added 2 new variants:
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Added parity protection in Stratix V GX devices.
Added speed grade information for Cyclone IV GX and included a second entry for
Cyclone IV GX running at 62.5 MHz in
Clarified qword alignment for request and completion TLPs for Avalon-ST interfaces.
Added table specifying the Total RX buffer space, the RX Retry buffer size and Maximum
payload size for devices that include the hard IP implementation.
Recommended that designs specify may eventually target the HardCopy IV GX device,
specify this device as the PHY type to ensure compatibility.
Improved definitions for hpg_ctrler signal. This bus is only available in root port mode. In
the definition for the various bits, changed “This signal is” to “This signal should be.”
Removed information about Stratix GX devices. The PCI Express Compiler no longer
supports Stratix GX.
Removed appendix describing test_in/test_out bus. Supported bits are described in
Chapter 5, IP Core
Moved information on descriptor/data interface to an appendix. This interface is not
recommended for new designs.
Clarified use of tx_cred for non-posted, posted, and completion TLPs.
Corrected definition of Receive port error in
Removed references to the PCI Express Advisor. It is no longer supported.
Reorganized entire User Guide to highlight more topics and provide a complete walkthough
for the variants created using the MegaWizard Plug-In Manage design flow.
Support for an integrated PCI Express hard IP endpoint that includes all of the reset and
calibration logic.
Support for a basic PCI Express completer-only endpoint with fixed transfer size of a
single dword. Removed recommended frequencies for calibration and reconfiguration
clocks. Referred reader to appropriate device handbook.
Interfaces.
Changes Made
Table 1–9 on page
Table 12–2 on page
1–14.
December 2010 Altera Corporation
12–2.
Additional Information
Revision History
SPR